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使用As-Sb异质结的隧穿晶体管的新进展
发表时间:2013-04-07 阅读次数:2680次

        隧穿晶体管(Tunneling FET)作为深亚微米工艺中MOS晶体管的潜在替代者,近些年来逐渐成为了研究的热点。相比于MOS晶体管,隧穿晶体管具有小亚阈值摆幅(SS Swing)、低漏电流(Low Leakage Current)的特点。传统硅基的TFET限于高隧穿能带阻挡层(Tunneling effective barrier),其驱动电流相较于MOS晶体管要小2个数量级。这个弱点限制了隧穿晶体管的在实际生产中的应用。为了克服这个弱点,窄禁带和异质结结构被引入作为TFET的源(Source)来减少隧穿势垒的高度(1, 2)。

        文献研究了隧穿势垒高度对TFET 驱动电流的影响。该小组通过改变 As-Sb合金中各成分的组分比例制造了各种不同高度的隧穿阻挡层(3),结构如图 1 所示,其Ebeff分别为0.31eV和0.25eV,而不采用异质结的AsSb合金其Ebeff则达到了0.74eV(4)。

        该小组制备的n-channel TFET的TEM图如图 2(a)所示,是一个侧向的垂直TFET结构。栅介质采用了Al2O3和HfO2的叠层Ald High-K工艺,异质结采用了固体源的分子束外延工艺。测试结果如图 2 所示,随着Ebeff的减小,驱动电流相应增大,最高增益达到了253%。除此之外,该研究小组还采用了更薄的栅介质来增强栅极对沟道的控制力,且实验结果也证实了这种设想,驱动电流获得了进一步的提高,达到了同质结的350%。由于使用了异质结结构,隧穿势垒的宽度在相同Vd偏置下相比于同质结结构已经缩小,Delta Vd对于隧穿势垒宽度的影响也会减小,因此漏至隧穿结变窄(Drain induced barrier thinning,DIBT)效应也会降低,如图 3(c)中DIBT效应减小了65%。相较于他人的研究(表 1),该文献获得了良好的结果:低Ebeff,薄栅介质层的异质结TFET展现了良好的亚阈值摆幅特性,高开关比特性,大驱动电流特性。

        该小组的实验展现了异质结结构在提高TFET 开关比、驱动电流、亚阈值摆幅中发挥的作用,为新型高性能TFET制备打下了基础,具有良好的指导意义。

图 3(a)SS 性能,(b)Drive-Current 性能,(C)DIBT效应,(D)模拟的能带和BTBT隧穿率。

表 1 本论文成果与他人成果对比

 

 

参考文献

1.  Mookerjea S, Mohata D, Krishnan R, Singh J, Vallett A, Ali A, et al., editors. Experimental demonstration of 100nm channel length In0.53Ga0.47As-based vertical inter-band tunnel field effect transistors (TFETs) for ultra low-power logic and SRAM applications. Electron Devices Meeting (IEDM), 2009 IEEE International; 2009.
2.  Dewey G, Chu-Kung B, Boardman J, Fastenau JM, Kavalieros J, Kotlyar R, et al., editors. Fabrication, characterization, and physics of III–V heterojunction tunneling Field Effect Transistors (H-TFET) for steep sub-threshold swing. Electron Devices Meeting (IEDM), 2011 IEEE International; 2011.
3.  Birner S, Zibold T, Andlauer T, Kubis T, Sabathil M, Trellakis A, et al. nextnano: General Purpose 3-D Simulations. Electron Devices, IEEE Transactions on. 2007;54(9):2137-42.
4.  Verhulst AS, Vandenberghe WG, Maex K, Groeseneken G. Boosting the on-current of a n-channel nanowire tunnel field-effect transistor by source material optimization. Journal of Applied Physics. 2008;104(6):064514--10.

 

英文摘要:  
       In this letter, we experimentally demonstrateenhancement in drive current ION and reduction in drain-inducedbarrier thinning (DIBT) in arsenide–antimonide staggered-gapheterojunction (hetj) tunnel field-effect transistors (TFETs) byengineering the effective tunneling barrier height Ebeff from 0.58to 0.25 eV. Moderate-stagger GaAs0.4Sb0.6/In0.65Ga0.35As(Ebeff = 0.31 eV) and high-stagger GaAs0.35Sb0.65/In0.7Ga0.3As (Ebeff = 0.25 eV) hetj TFETs are fabricated,and their electrical results are compared with the In0.7Ga0.3Ashomojunction (homj) TFET (Ebeff = 0.58 eV). Due to the 57%reduction in Ebeff , the GaAs0.35Sb0.65/In0.7Ga0.3As hetj TFETachieves 253% enhancement in ION over the In0.7Ga0.3Ashomj TFET at VDS = 0.5 V and VGS − VOFF = 1.5 V. Withelectrical oxide thickness (Toxe) scaling from 2.3 to 2 nm, theenhancement further increases to 350%, resulting in a record highION of 135 μA/μmand 65%reduction in DIBT at VDS = 0.5 V.

 

文献地址:

http://ieeexplore.ieee.org/xpl/articleDetails.jsp?tp=&arnumber=6313884&contentType=Journals+%26+Magazines&queryText%3DBarrier-Engineered+Arsenide%E2%80%93Antimonide

 

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